The present invention relates to substrate processing. More specifically, the present invention relates to the deposition of a planarized passivation layer.
Interconnections of semiconductor devices on integrated circuits are typically made by metal conductors, which in some cases are narrow, closely spaced metal lines. The use of two (or more) levels of such metal conductors is not uncommon. After the last layer of metal conductor is deposited, one of the final fabrication steps is the deposition of an insulating layer, also referred to as a passivation layer. The passivation layer protects the underlying layers from chemical action, corrosion, and/or mishandling during the packaging process by protecting the device from moisture, contamination, and physical contact. Several techniques are currently used to apply passivation layers.
One technique used to create passivation layers employs spin-on glass (SOG). The most commonly used SOG materials are SiO.sub.x -based polysiloxanes. SOG films are typically applied to a predeposited oxide as a liquid that covers a substrate's features. As with photoresist, the material is dispensed on a wafer and spun with a rotational speed that determines the SOG thickness. The film is then cured and, optionally, etched back to smooth the surface. The SOG may be capped to protect it during further processing. However, silicon oxide-based SOG can have detrimental effects on circuits, most of them related to its absorption of water. The presence of water in SOG can create problems such as mobile protons and large increases in the dielectric constant, resulting in an increase in parasitic capacitance and performance degradation.
A more common method of forming a passivation layer is by the chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions produce a desired film. Another CVD technique is plasma-enhanced CVD (PECVD). PECVD techniques promote excitation and/or dissociation of the reactant gases by the application of energy, such as radio frequency (RF) energy, to excite the reactant gases, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place. This lowers the process's operating temperature, making the PECVD process well-suited to depositing insulating layers over deposited metal layers (e.g., passivation layers).
PECVD processes used to deposit passivation layers often employ some type of glass material. For example, a PECVD technique may be used to deposit a passivation layer of silicon nitride (Si.sub.3 N.sub.4) or undoped silicate glass (USG). Optionally, dopants may be included to improve step coverage, dielectric constant, and other film characteristics. Such doped passivation layers include the use of materials such as phosphosilicate glass (PSG). One common planarization technique is the fabrication of a multilevel passivation layer. The structure is formed, for example, by depositing a silicon oxide layer, followed by a silicon nitride layer. To maintain high throughput, such processes use deposition rates of 4800 .ANG./min or more. However, the gap-fill capabilities of such films may be insufficient for use in some circumstances.
As device sizes have become smaller and integration density has increased, issues that were not previously considered important by the industry have become of concern. For example, as circuit densities increase, the spacing between adjacent metal conductors decreases, which causes an increase in the ratio of the height of adjacent conductors to their separation, commonly referred to as the aspect ratio. An increase in the aspect ratio is accompanied by an increase in the likelihood that a deposited insulating layer will not conform to and completely fill the gap between conductors. Thus, as an insulating layer is deposited, an undesirable void may form within the layer between adjacent conductors. Typically, voids are formed when the dielectric deposits on the upper portion of adjacent metal vertical side walls contact each other before the bottom of the gap is filled. These voids may trap air, or, if photolithographic patterning is subsequently performed (e.g., to form contact pads), they may trap the photoresist material used to transfer the pattern onto the passivation layer. The trapped photoresist may then be outgassed during subsequent heating of the substrate. Moreover, such voids can create (and propagate) cracks in the various layers.
A solution to the gap-fill problem is to perform a three-step deposition/etch-back/deposition (DED) process. In this three-step process, an insulating layer is first partially deposited over a metal layer. Next, a physical etch-back step is performed in which the deposited insulation layer is bombarded with argon or a similar gas in a sputtering step. The argon sputtering etches away some of the excess deposits that might otherwise contribute to void formation. After completion of the physical etch-back, deposition is completed in the third step. The three-step deposition/etch-back/deposition process provides improved gap-fill capabilities that are suitable for many applications, including the formation of passivation layers.
However, the DED process is a slow, complex operation in comparison with the SOG and PECVD methods described previously. This complexity adds to the cost of devices thus fabricated (due to the increase in processing needed to produce the device), reduces throughput, and increases the probability of equipment failure. Moreover, as devices become even smaller, better gap-fill capabilities are likely to be desirable for some applications. Hence, there is a need for a method and an apparatus that further improve the gap-fill capability and planarity of present passivation layers. Preferably, these techniques should operate in a fast, simple, and cost-effective manner.